Techniques for reducing the processing time of web based transactions include scale out and scale up strategies in which additional computing resources are made available to handle a transaction workload. Both of these strategies typically include increasing random access memory, typically dynamic random access memory (DRAM), for the purpose of building larger in-memory caches, whether centralized or distributed, to significantly decrease access times to data and web objects. As systems are implemented with increasing amounts of DRAM, the amount of energy consumed by DRAM memory can increase.
DRAM cells need to be refreshed from time-to-time to restore leaking charge and thus maintain their logic state. That is, it is necessary to perform a specified number of refresh operations within a predetermined period of time in order to hold data in DRAM memory in an activated state. DRAM memory devices have two main types of refresh operation modes. One is an auto-refresh operation mode for normal DRAM memory access. The other is a self-refresh operation mode, in which the refresh operation is performed solely to hold data without accessing the DRAM memory device. The self-refresh operation mode is a mode of operation that provides a function of automatically executing the refresh operation inside the DRAM memory device. During operation in self-refresh operation mode, it is possible to hold data with much less power than when a DRAM device is activated for access by an interface unit outside of the DRAM memory device. Various DRAM-level power management schemes allow for different portions of a DRAM memory device to be in either auto-refresh mode or in a self-refresh power-saving mode. There is a performance penalty when accessing a memory location that is in self-refresh mode.
Because not all data in memory is accessed or updated at the same frequency, additional operating system level schemes have been developed to identify low-access data and have this data in memory locations that are in self-refresh mode, thus reducing the memory energy requirements.